Extended Frequency-Directed Run-Length Code with Improved Application to System-on-a-Chip Test Data Compression

One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0’s. In this work, we demonstrate that higher test data compression can be achieved based on encoding both runs of 0’s and 1’s. We propose an extension to the FDR code and demonstrate by experimental results its effectiveness in achieving higher compression ratio

Extended Frequency-Directed Run-Length Code with Improved Application to System-on-a-Chip Test Data Compression

One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0’s. In this work, we demonstrate that higher test data compression can be achieved based on encoding both runs of 0’s and 1’s. We propose an extension to the FDR code and demonstrate by experimental results its effectiveness in achieving higher compression ratio

Extended Frequency-Directed Run-Length Code with Improved Application to System-on-a-Chip Test Data Compression

One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0’s. In this work, we demonstrate that higher test data compression can be achieved based on encoding both runs of 0’s and 1’s. We propose an extension to the FDR code and demonstrate by experimental results its effectiveness in achieving higher compression ratio

ON IMPROVING THE EFFECTIVENESS OF SYSTEM-ON-ACHIP TEST DATA COMPRESSION BASED ON EXTENDED FREQUENCY DIRECTED RUN-LENGTH CODES

One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0’s. In this work, we demonstrate that higher test data compression can be achieved based on encoding both runs of 0’s and 1’s. We propose an extension to the FDR code and demonstrate by experimental results its effectiveness in achieving higher compression ratio

Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning

The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. With current trends, partitioning with multiple objectives which includes power, delay and area, in addition to minimum cut is in vogue. In this paper, we engineer three iterative heuristics for the optimization of VLSI netlist bi-Partitioning. These heuristics are based on Genetic Algorithms (GAs), Tabu Search (TS) and Simulated Evolution (SimE). Fuzzy rules were incorporated in order to handle the multiobjective cost function. For SimE, fuzzy goodness functions are designed for delay and power, and proved efficient. A series of experiments are performed to evaluate the efficiency of the algorithms. ISCAS-85/89 benchmark circuits are used and experimental results are reported and analyzed to compare the performance of GA, TS and SimE. Further, we compared the results of the iterative heuristics with a modified FM algorithm, named PowerFM, which targets power optimization. PowerFM performs better in terms of power dissipation for smaller circuits. For larger sized circuits SimE outperforms PowerFM in terms of all three, delay, number of net cuts, and power dissipation

EVOLUTIONARY HEURISTICS FOR MULTIOBJECTIVE VLSI NETLIST BI-PARTITIONING

The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partitioning especially in VLSI, and has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut was of prime importance. Furthermore, with current trends partitioning has become a multi-objective problem, where power, delay and area in addition to minimum cut, need to be optimized. In this paper we employ two iterative heuristics for the optimization of VLSI Netlist Bi-Partitioning. These heuristics are based on Genetic Algorithms (GAs) and Tabu Search (TS) [sadiq et al., 1999] respectively. Fuzzy rules are incorporated in order to design a multiobjective cost function. Both the techniques are applied to ISCAS-85/89 benchmark circuits and experimental results are reported and compared

Evolutionary Algorithms for VLSI Multiobjective Netlist Partitioning

The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. With current trends, partitioning with multiple objectives which includes power, delay and area, in addition to minimum cut is in vogue. In this paper, we engineer three iterative heuristics for the optimization of VLSI netlist bi-Partitioning. These heuristics are based on Genetic Algorithms (GAs), Tabu Search (TS) and Simulated Evolution (SimE). Fuzzy rules are incorporated in order to handle the multiobjective cost function. For SimE, fuzzy goodness functions are designed for delay and power, and proved efficient. A series of experiments are performed to evaluate the efficiency of the algorithms. ISCAS-85/89 benchmark circuits are used and experimental results are reported and analyzed to compare the performance of GA, TS and SimE. Further, we compared the results of the iterative heuristics with a modified FM algorithm, named PowerFM, which targets power optimization. PowerFM performs betterintermsofpowerdissipationforsmallercircuits.Forlargersizedcircuits SimE outperforms PowerFM in terms of all three, delay, number of net cuts, and power dissipation